IC Verification and Validation Engineer (m/v)

By | Februar 20, 2021
  • Überall

Job title: IC Verification and Validation Engineer (m/v)

Company: Actief Interim

Job description:

  • Responsible for the quality of IP and/or SoC firmware driven and UVM verification, validation characterization of wireless communication systems
  • Creation of verification, validation and characterization requirements, development and execution of respective verification/validation and characterizations plans on time
  • Develop C based FW, tests and verification environments, and coverage using UVM methodologies to meet verification targets
  • Verification of IPs and subsystems by means of Formal Verification methods and techniques: System Verilog Assertions and tools
  • Develop and reuse existing FW in pre and post-silicon environments such as FPGA prototypes, ASIC simulators and lab environments
  • Investigate issues, debug designs, FW tests and verification benches (RTL and Gate Level) using simulation tools and board (Silicon and FPGA)
  • Verification and validation flow implementation and updates targeting EDA tools
  • Degree in Electrical or Communication Engineering with at least 2 years of experience
  • Expertise in embedded FW development and associated flow for ARM based SoC (subsystems/top-level) used in verification, validation and characterization for wireless communication systems (Wifi, LTE, GPS/GNSS)
  • Expertise with HDL languages for verification (Verilog, VHDL, SystemVerilog)
  • Expertise in high-level programming languages (C/C++) for ARM processors
  • Experience with IC validation using FPGA prototyping and/or silicon characterization platforms
  • Experience in Verification methodologies (FW driven, UVM, Coverage) to develop testbenches, verification environments, verification components. Expertise in UVM and FW are big advantage.
  • Team player with the ability to work independently and precisely
  • Good verbal and written communications skills in English
  • Holder of a valid European work permit will be an asset
  • A challenging position within an international work environment in a successful company
  • A openended employment
  • A competitive salary and extra legal benefits

Expected salary:

Location: Heverlee, Vlaams Brabant

Job date: Sat, 20 Feb 2021 06:51:27 GMT

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